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73M2910L microcontroller april 2000 description the 73M2910L high performance micro-controller is based on the industry standard 8-bit 8032 implemented in an advanced submicron cmos process. the processor has the attributes of the 8032, including instruction cycle time, uart, timers, interrupts, 256 bytes of on-chip ram and programmable i/o. the architecture has been optimized for low power portable modem or communication applications by integrating unique features with the core cpu. a key feature is a user friendly hdlc packetizer, accessed through the special function registers. it has a serial i/o, hardware support for 16 and 32-bit crc, zero insert/delete control, a dedicated interrupt and a clear channel mode for by-passing the packetizer. other features include additional user programmable i/o with programmable bank select and chip select logic, designed to eliminate board level glue logic. it also includes two general-purpose input ports with programmable wakeup capability. for devices that require non-multiplexed address and data buses, eight latched outputs for the low byte of the address are available. (continued) features ? 8032 compatible instruction set ? 44 mhz operation from 3.3 to 5.5v ? hdlc support logic (packetizer, 16 and 32 crc, zero id) ? 24 pins for user programmable i/o ports ? 8 pins programmable chip select logic or i/o for memory mapped peripheral eliminating glue logic ? 3 external interrupt sources (programmable polarity) ? 16 dedicated latched address pins ? multiplexed data/address bus ? instruction cycle time identical to 8032 ? buffered oscillator (or osc/2) output pin ? 1.8432 mhz uart clock available ? bank select circuitry to support up to 128k of external program memory ? also available in 100-lead qfp and 100-pin pga packages block diagram (2:0) usr 1.0 usr 1.1 usr 1.2 usr 1.3 rxd txd ptxclk ptxd prxclk prxd oscin oscout clkout1 clkout2 ale a (15:0) d (7:0) usr5 (1:0) csb (7:0) usr3 (7:0) usr2 (7:0) usr1 (7:0) sfr bus time gen cpu mem i/o ctrl usr i/o usr i/o ram 256 x 8 hdlc uart timers interrupt control add/data io
73M2910L microcontroller 2 description (continued) the 73M2910L has two extra interrupt sources, an external interrupt and a hdlc interrupt. the hdlc interrupt has two registers associated with it; the hdlc interrupt register which is used to determine the source of the interrupt, and the hdlc interrupt enable register that enables the source of the interrupt. the state of the external interrupts can be read through a register allowing the interrupt pins to be used as inputs. the interrupt pins int0 and int1 can be either negative edge, positive edge or level triggered. the int2 pin is always edge triggered. two buffered clock outputs have been added to support peripheral functions such as uarts, modems and other clocked devices. the main internal processor clock frequency can be divided by 2 for power conservation in functional modes that only require half the clock speed. additional internal special function registers are used for firmware control over the hdlc packetizer, the clocks and the programmable i/o ports. to accommodate processor peripherals when operating at higher frequencies, the processor?s timing has been altered to allow more address setup time for slower peripheral program rom and memory mapped peripherals. for low power applications the 73M2910L supports two power conservation modes: idle and power-down. in the power-down state the total current consumption is less than 10 a at room temperature. developer?s note: the 73M2910L is also available in a 100-pin pga package for system developers. the pga package is more convenient and reliable for development emulation systems than the other package styles. emulation systems for the 73M2910L are available through signum systems, 11992 challenger court, moorpark, ca 93021 (805) 523-9774. 8032 reference this document will describe the features unique to the 73M2910L. please refer to a 8032 programmer?s guide, architectural overview and hardware description for details on the instruction set, timers, uart, interrupt control, and memory structure.
73M2910L microcontroller 3 register description interrupts the core chip provides 8 sources of interrupt; 3 external interrupts, 3 timer interrupts, a serial port interrupt, and an hdlc interrupt. an external interrupt and an hdlc interrupt are unique to the 73M2910L. they do not exist in a normal 8032 product. previously unused bits in the ie and ip registers are now serving functions for these additional interrupt sources. the interrupt vector addresses are as follows: source vector address int) (ie0) 003h tf0 00bh int! (ie1) 013h tf1 01bh ri + ti 023h tf2 + exf2 02bh int@ - added interrupt 033h hdlc - added interrupt 03bh the external interrupt sources, int(2:0), come from dedicated input pins. the apparent polarity of these pins is individually controlled by bits in a special interrupt direction register, idir (address a9). the interrupt pins int! and int) can be either edge or level generated interrupts as indicated by bits 1 and 3 in the tcon register (address 88). pin int@ is always an edge generated interrupt. a flag is set when a falling transition (rising if idir bit 2 is set) on this pin is detected. this flag is automatically cleared when the interrupt is processed. interrupt enable register (ie) sfr address 0a8h bit addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ea ex2 et2 es et1 ex1 et0 ex0 note: bit 6 differs from the 8032. this is a reserved bit in the 8032 and is used as a mask bit for external interrupt 2 in the core implementation. when bit 6 is set to a 0, external interrupt 2 is disabled. the mask bit for the hdlc interrupt source is bit 0 of the hdlc control register. interrupt priority register (ip) sfr address 0b8h bit addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 phdlc px2 pt2 ps pt1 px1 pt0 px0 note: bit 6 and bit 7 differ from the 8032. these are reserved bits in the 8032 and are used to determine the priority of external interrupt 2 and the hdlc in the core implementation. when bit 6 is set to a 1, the interrupt is set to the higher priority level.
73M2910L microcontroller 4 interrupts (continued) external interrupt direction register (idir) sfr a ddress 092h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 int@ int! int) intd2 intd1 intd0 these bits determine the polarity of the corresponding external signals int(2:0) which will result in an interrupt and will also allow the user to directly read the logic level at the pads int(2:0). bits (5:3) int(2:0) bits (5:3) are read only bits that reflect the logic value at the corresponding pin. the value is not affected by bits (2:0). bits (2:0) interrupt polarity control if the bit is set to a 0, a falling edge will trigger the interrupt. if the bit is set to a 1, a rising edge will trigger the interrupt. also, if the bit is set to a 1, level generated interrupts will occur when the corresponding pin is high and the internal pin signal to the timer controls will be inverted. bits 6 and 7 will always be read as 0?s. clock control register sfr address 0dah byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 activity clk1 ctrl1 mclk ctrl clk2en clk2 ctrl1 clk2 ctrl0 clk1en clk1 ctrl0 these bits determine the behavior at the clk1out and clk2out pins and allow the user to divide the main internal processor clock frequency by two for power conservation. bit 7 bit 7 is an activity bit. it is cleared by a read of this register. if the activity bit is set it will prevent the 73M2910L from entering sleep mode. bit 6 when bit 6 = 1, clk1out will be osc/1.5 if bit 1 is a 1 and bit 0 is 0. bit 5 clock out 0osc 1osc/2 bit 5 master clock control when bit 5 is set to a 1 the internal processor clock is the oscillator frequency divided by 2. if this bit is a 0, the processor clock is the same frequency as the oscillator?s.
73M2910L microcontroller 5 bit 4 clock 2 output enable bit 4 enables the clock at the clock 2 output pin if it is set to a 1. the clock 2 pin output is held to a 0, by writing this bit to a 0. this will reduce system power if the clock pin is not used or if a power reduction mode is required. bits 3,2 clock 2 output control these bits determine the oscillator divisor for the clock 2 output pin. they were designed to provide a 1.8432 mhz clock for an external uart given an oscillator frequency of 11.0592 mhz, 22.1184 mhz, 18.432 mhz, or 13.824 mhz. bit 3 bit 2 clk 2 out osc frequency 0 0 osc/7.5 13.824 mhz 0 1 osc/6 11.059 mhz 1 0 osc/12 22.118 mhz 1 1 osc/10 18.432 mhz bit 1 clock 1 output enable bit 1 enables the clock at the clock 1 output pin if it is set to a 1. the clock pin output is held to a 0, by writing a 0 to this bit. this will reduce system power if the clock pin is not used or if a power reduction mode is required. bit 6 is cleared to a 0 upon a reset. bit 0 clock 1 output control bit 0 controls the frequency of the clock 1 output pin. the clock output is either the oscillator?s output signal divided by two or a buffered oscillator output signal. power saving modes low power modes the 73M2910L supports two power conservation modes, which are controlled by the pcon.1 and pcon.0 control bits of the pcon register. if pcon.0 is set, the 73M2910L will go into a power saving mode where the oscillator is running, clocks are supplied to the uart, timers, hdlc, and interrupt blocks, but no clocks are supplied to the cpu. instruction processing and activity on the address and data ports is halted. normal operation is resumed when an unmasked interrupt is requested or when a reset occurs. if pcon.1 is set, the 73M2910L goes into its lowest power mode where the oscillator is halted. the total current consumption in this state should be less than 10 a. the 73M2910L will start its oscillator and begin to return to normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of an unmasked external interrupt from pins int(2:0) is detected, or when the usr5 (1:0) pins change to a state according to the usr5 port register. edges used in wakeup modes are not filtered in the 73M2910L, so the user must be cautious of noise or small glitches inadvertently waking up the chip. from the time the edge that results in the wake up occurs, to the point at which an instruction is executed, depends on the oscillator start-up time. three good oscillator pulses must be detected before the main internal clocks are generated. during power-down mode, both the ale and psen pins are pulled high since these signals often provide the output enable and chip enable for the rom (active low). this ensures that the external components are in their lowest power state.
73M2910L microcontroller 6 register description (continued) usr programmable i/o port control usr1, usr2, usr3, usr4, usr5 the core chip provides 32 user i/o pins. each pin is programmed separately as either an input or as an output by a bit in a direction register. if the bit in the direction register is set to a 1, the i/o control will treat the corresponding pin as an input. if it is a 0, the pin will be treated as an output whose value is determined by the port data register. the usr1 and usr2 port registers are accessed through the internal sfr bus. the usr3 and usr4 ports are accessed through the external memory bus by a movx instruction. the usr4 port provides the user with an automatic chip select function if selected by the user. if the user does not require some (or any) of the chip select pin options, he may program the usr4 port pins to operate in the same way as usr3 port pins. the usr data register contents determine pin values if chosen as an output. when reading from the data register?s sfr address, the pin logic values are returned as data except when the port address is the destination address for a read-modify-write instruction. in this case, the latched register values are returned as data. when reading data from a data register that is mapped in the external memory space, the pin values are always returned as data. the usr5 register allows for 2 additional input pins. in normal operation these pins can be used as general purpose inputs. in power-down mode, the user can program either rising or falling transitions or logical combinations of these pins to wake up the chip. usr 1 port usr1 data sfr address 90h bit addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr1.7 usr1.6 usr1.5 usr1.4 usr1.3 usr1.2 usr1.1 usr1.0 bits in this register will be asserted on the usr1(7:0) pins if the corresponding direction register bit is a 0. reading this sfr?s address will return data reflecting the values of pins usr1(7:0) except when address 90h is the destination address for a read-modify-write instruction. in this case, the latched register values are returned as data. usr1 port signals are also used as timer controls. in applications where the external signals are required for timer count modes, the corresponding port pin should be configured as an input. usr1.0 bit = timer0 t0 pin usr1.1 bit = timer1 t1 pin usr1.2 bit = timer2 t2 ex pin usr1.3 bit = timer2 t2 pin usr1 port direction (dir1) sfr address 91h byte addressable reset state ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir1.7 dir1.6 dir1.5 dir1.4 dir1.3 dir1.2 dir1.1 dir1.0 this register is used to designate the usr1 pins as either inputs or outputs. if the register bit is reset to a 0, the corresponding usr1 pin is programmed as an output that will be driven by the corresponding usr1 data register bit. if the register bit is a 1, the corresponding pin will be treated as an input.
73M2910L microcontroller 7 after a reset, the usr1 pins will present a high impedance output state and the input values will not be driven from the pin, but will be driven to a 1 internally. the pins will assume normal i/o operation once the processor has written the port direction register. this feature will ensure a low current state at reset (you don?t want to drive out against external inputs, and you don?t want floating inputs). usr2 port usr2 port data sfr address 0d8h bit addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr2.7 usr2.6 usr2.5 usr2.4 usr2.3 usr2.2 usr2.1 usr2.0 bits in this register will be asserted on the usr2(7:0) pins if the corresponding direction register bit is a 0. reading this sfr?s address will return data reflecting the values of pins usr2(7:0) except when address 0d8h is the destination address for a read-modify-write instruction. in this case, the latched register values are returned as data. usr2 port direction (dir2) sfr address 0d9h byte addressable reset state ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir2.7 dir2.6 dir2.5 dir2.4 dir2.3 dir2.2 dir2.1 dir2.0 this register is used to designate the usr2 pins as either inputs or outputs. if the register bit is reset to a 0, the corresponding usr2 pin is programmed as an output that will be driven by the corresponding usr2 i/o data register bit. if the register bit is a 1, the corresponding pin will treated as an input. after a reset, the usr2 pins will present a high impedance output state and the input values will not be driven from the pin, but will be driven to a 1 internally. the pins will assume normal i/o operation once the processor has written the port direction register. this feature will ensure a low current state at reset (you don?t want to drive out against external inputs, and you don?t want floating inputs). usr3 port usr3 port data external address 0000h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr3.7 usr3.6 usr3.5 usr3.4 usr3.3 usr3.2 usr3.1 usr3.0 bits in this register will be asserted on the usr3(7:0) pins if the corresponding direction register bit is a 0. reading this sfr?s address will return data reflecting the values of pins usr3(7:0). if the bank select feature is chosen, the usr3.7 pin acts as address bit 17 and usr3 data bit 7 is ignored.
73M2910L microcontroller 8 usr3 port (continued) usr3 i/o port direction (dir3) external address 0001h byte addressable reset state ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir3.7 dir3.6 dir3.5 dir3.4 dir3.3 dir3.2 dir3.1 dir3.0 this register is used to designate the usr3 pins as either inputs or outputs. if the register bit is reset to a 0, the corresponding usr3 pin is programmed as an output that will be driven by the corresponding usr3 data register bit. if the register bit is a 1, the corresponding pin will be treated as an input. after a reset, the usr3 pins will present a high impedance output state and the input values will not be driven from the pin, but will be driven to a 1 internally. the pins will assume normal i/o operation once the processor has written the usr3 port direction register. this feature will ensure a low current state at reset. if the bank select feature is chosen, usr3.7 pin is forced to be an output. bank select (bnksel) external address 0002h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b7 b6 b5 b4 b3 bsen bs1 bs0 this register is used to accommodate systems where more than 64 kbytes (up to 128 kbytes) of program memory are required. pin usr3.7 acts as an address pin, a16, if bsen is set to a 1 and the processor is fetching an instruction and not data memory. if bsen is set to a 1, a15 is also modified during instruction fetches as shown below. if bsen is a 0, no alterations to address bit a15 are made, and pin usr3.7 is a function of usr3 bit 7 and dir3 bit 7. bits (7:3) are general purpose read/write register bits. a15 value of the 16th address bit as it appears at pin a15. a15? address from port 2 internal logic, the value that will appear as the most significant address bit if no bank select feature is chosen. a16 value of the 17th and msb of the instruction address seen at the usr3.7 port pin, if the bank select feature is selected. if the bank select feature is not selected, usr3.7 acts as a normal usr3 i/o port pin.
73M2910L microcontroller 9 bsen bs1 bs0 a15? a15 a16 address 0 0 * * * * 0 1 0 1 usr3.7 usr3.7 0k - 32k 32k - 64k 1 1 0 0 0 0 0 1 0 1 0 0 0k- 32k 32k - 64k 1 1 0 0 1 1 0 1 0 0 0 1 0k - 32k 64k - 96k 1 1 1 1 0 0 0 1 0 1 0 1 0k - 32k 96k- 128k 1 1 1 1 1 1 0 1 0 0 0 1 0k- 32k 64k - 96k * = don?t care figure 1: bank select 64k - 96k 0 - 32k bank 3 bank 2 bank 1 bank 0 bank 2 is selected if a15' is a 1, fetches will come from bank 2 bank 2 will overlay bank 1 that is all fetches that would normally occur from bank 1 will come from bank 2 96k - 128k 32k - 64k example: bank 2 is selected bsen = 1, bs1 = 0, bs0 = 1
73M2910L microcontroller 10 usr programmable i/o (continued) usr4 port usr4 port data external address 0003h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr4.7 usr4.6 usr4.5 usr4.4 usr4.3 usr4.2 usr4.1 usr4.0 bits in this register will be asserted on the usr4(7:0) pins if the corresponding direction register bit is a 0 and if the corresponding bit in the chip select enable register, 0005, is set to a 0. reading this register will return data reflecting the values of pins usr4(7:0). usr4 i/o port direction (dir4) external address 0004h byte addressable reset state ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dir4.7 dir4.6 dir4.5 dir4.4 dir4.3 dir4.2 dir4.1 dir4.0 this register is used to designate the usr4 pins as either inputs or outputs. if the register bit is reset to a 0, the corresponding usr4 pin is programmed as an output that will be driven by the corresponding usr4 i/o data register bit if the corresponding bit in the chip select enable register, 0005, is set to a 0. if the register bit is a 1, the corresponding pin will treated as an input only if the corresponding bit in register 0005 is set to a 0. after a reset, the usr4 pins will act as chip select outputs. usr4 port chip select enable (csen) external address 0005h byte addressable reset state ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csen 7 csen 6 csen 5 csen 4 csen 3 csen 2 csen 1 csen 0 this register is used to designate the usr4 pins as either user programmable i/os or as chip select (cs0b - cs7b) functions on a pin by pin basis. this feature is designed to help reduce external glue logic for peripheral memory mapped devices. the chip select function is programmed by setting the appropriate bits in the csen register. when a chip select pin is enabled by setting the corresponding csen bit to a 1, all data and direction information from registers 0003 and 0004 for this bit are ignored and the selected port becomes an output. if the bit is reset to a 0, the pin will be treated as a normal programmable user i/o pin as defined by registers 0003 and 0004. the chip select pins have a defined memory map. the intent is that the outputs can be wire or?ed together for a flexible selection of peripheral chip selects. all chip selects will be disabled (forced to a logic 1. it is assumed that all chip selects are active low) after the read or write is completed, and the appropriate chip select will be enabled as the next new external addresses is asserted. after a reset, the csb pull-up devices are all enabled, that is, all chip select outputs are high. users must account for this if these pins are intended to be general purpose i/os.
73M2910L microcontroller 11 the chip selects partition a 64k memory space as follows: chip select pin address # bytes reserved for internal use 0000h - 00ffh 256 cs0 (usr4.0) 0100h - 01ffh 256 cs1 (usr4.1) 0200h - 03ffh 512 cs2 (usr4.2) 0400h - 07ffh 1k cs3 (usr4.3) 0800h - 0fffh 2k cs4 (usr4.4) 1000h - 1fffh 4k cs5 (usr4.5) 2000h - 3fffh 8k cs6 (usr4.6) 4000h - 7fffh 16k cs7 (usr4.7) 8000h - ffffh 32k note:external addresses 0000h-00ffh may not be read. these are reserved for 73M2910L internally defined registers usr5 port usr5 port register external address 0006h byte addressable reset state 60h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 usr5en usr5.0 usr5.1 pol5.0 pol5.1 acte0 acte1 and01 this register allows user programmable wakeup capability. if this is not required, this register can be used to read external signals at the usr5.1 and usr5.0 pins. bit 7 usr5 input port enable bit 7 is used to enable the usr5.1 and usr5.0 input circuitry. if this bit is a 0, the usr5 pin output circuitry is driven to a known level internally and any signal level at the pin is ignored. when set to a 1 the pin input circuitry is enabled and the values of these pins are reflected in bits 6 and 7. if these pins are not connected at the board level, this bit should remain at a 0 to keep the pin input circuitry from drawing unnecessary current. the usr5 register can be programmed such that a transition (bit 4 determines rising or falling) of usr5.0, a transition (bit 3 determines rising or falling) of usr5.1, or the logical combination of usr5.0 (bit 4 determines high or low level) and usr5.1 (bit 3 determines high or low level) can wakeup the processor from its power-down mode. bit 6 usr5.0 bit 6 reflects the value of chip pin usr5.0 if the usr5en bit is set to a 1. bit 5 usr5.1 bit 5 reflects the value of chip pin usr5.1 if the usr5en bit is set to a 1.
73M2910L microcontroller 12 usr5 port (continued) bit 4 usr5.0 polarity bit 4 determines which edge or level is used in the wakeup detection circuit. a low level selects a rising transition and the true pin value of usr5.0 to the wakeup detection circuit. when this bit is set to a 1, a falling transition and complemented usr5.0 value is presented to the wakeup detection circuit. bit 3 usr5.1 polarity bit 3 determines which edge or level is used in the wakeup detection circuit. a low level selects a rising transition and the true pin value of usr5.1 to the wakeup combinatorial circuit. when this bit is set to a 1, a falling transition and complemented usr5.1 value is presented to the wakeup detection circuit. bit 2 usr5.0 edge activity enabled when bit 2 is set to a 1, a transition of usr5.0 of the appropriate level as dictated by bit 4, will wake up the processor. if this bit is reset to a 0, edge activity on this pin is ignored. bit 1 usr5.1 edge activity enabled when bit 1 is set to a 1, a transition of usr5.0 of the appropriate level as dictated by bit 3, will wake up the processor. if this bit is reset to a 0, edge activity on this pin is ignored. bit 0 combinatorial and of usr5.0 and usr5.1 level enabled when bit 0 is set to a 1, the value usr5.0 or its complimented value as dictated by bit 3, and?ed with the value usr5.1 or its complimented value as dictated by bit 2, will wake up the processor. if this bit is reset to a 0, the levels of usr5.0 and usr5.1 are ignored. usr5.0 usr5.1 bit 4 bit 3 bit 2 bit 1 bit 0 wakeup ****000no 0-1 * 0 * 1 * * yes 1-0 * 1 * 1 * * yes *0-1* 0 * 1 *yes *1-0* 1 * 1 *yes 0011* *1yes 1001* *1yes 0110* *1yes 1100* *1yes * = don?t care
73M2910L microcontroller 13 hdlc packetizer register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdlc control 0 (hdlc0) c0 wrxd wptxd txd prxd rxd ctrl1 rxd ctrl0 ptxd ctrl1 ptx ctrl0 hdlc control 1 (hdlc1) c1 reset ccit crc pre rxcrc32 rxcrc16 txcrc32 zero id hdlc inten hdlc tx control (htxc) c2 0 0 0 div16 clk send abort send crc send data send flag hdlc status (hstat) c3 inval crc32 inval crc16 tx underrun rx underrun inval flag abort detect idle detect flag detect hdlc int enable (hie) c4 tx rdy ie rx rdy ie tx rdy en rx rdy en inval flag ie abort ie idle ie flag ie hdlc int source (hint) c500000new status rx ready tx ready rx data (rxd) c6 rxdat7 rxdat6 rxdat5 rxdat4 rxdat3 rxdat2 rxdat1 rxdat0 tx data (txd) c7 txdat7 txdat6 txdat5 txdat4 txdat3 txdat2 txdat1 txdat0 figure 2: hdlc sfr registers hdlc control registers hdlc control register 0 (hdlc0) sfr address 0c0h bit addressable reset state 00xx 0000 b bits 5 and 4 are read only bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wrxd wptxd txd r prxd r rxd ctrl1 rxd ctrl0 ptx ctrl1 ptx ctrl0 this register controls the basic set-up of the dte and modem pins rxd, txd, prxd, and ptxd. bit 7 wrxd bit 7 allows the processor to write directly to the 73M2910L rxd output pin. the value of bit 7 will appear at the rxd pin only if bit 3 is a 1 and bit 2 is a 1. bit 6 wptxd bit 6 allows the processor to write directly to the 73M2910L ptxd output pin. the value of bit 6 will appear at the ptxd pin only if bit 1 is a 1 and bit 0 is a 0. bit 5 txd bit 5 is a read only bit that reflects the value at the 73M2910L txd input pin. bit 4 prxd bit 4 is a read only bit that reflects the value at the 73M2910L prxd input pin.
73M2910L microcontroller 14 hdlc control register 0 (hdlc0) sfr address 0c0h (continued) bits 3,2 rxd control bit 3 and bit 2 control the source of the 73M2910L rxd output pin. this output goes to the dte?s rs232 interface. the source of this signal can be the core?s uart txd output, the prxd output from a modem peripheral (clear channel), the dte?s txd (echo), or the value written into bit 7 of this register. bit 3 bit 2 rxd output 0 0 uart txd output 0 1 prxd buffered (clear channel) 1 0 txd buffered (echo) 11wrxd (bit 7) bits 1,0 ptxd control bit 1 and bit 0 control the source of the 73M2910L ptxd output pin. this output goes to the modem?s tx data input. the source of this signal can be the core?s hdlc tx output, the dte?s txd output (clear channel), or the value written into bit 6 of this register. bit 1 bit 0 ptxd output 0 0 hdlc tx output 0 1 txd buffered (clear channel) 10wptxd (bit 6) 110 hdlc control register 1 (hdlc1) sfr address 0c1h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdlc rst ccitt crc pre rxcrc 32 rxcrc 16 txcrc ctrl zero id hdlc inten this register controls the basic set-up of the hdlc block. this register will be written during initialization and not during normal message processing. bit 7 hdlc software reset when bit 7 is a 1, the hdlc circuit is reset and held in a low power state and no interrupts from the hdlc circuitry will be generated. when a 0 is written to this bit, the hdlc circuit will behave according to its control bits. bit 7 and the power-on-reset signal are or?ed together to form a reset signal for the hdlc block. bit 7 is cleared to a 0 upon a power-up-reset. bit 6 crc type control bit 6 selects the crc algorithm used in the 16-bit crc calculation. there are two types of 16-bit crcs commonly used, crc16 and the ccitt 16-bit crc. if this bit is set to a 1, the ccitt type is selected. bit 6 is cleared to a 0 upon a reset.
73M2910L microcontroller 15 bit 5 crc preset value bit 5 selects the reset value for the crc generator and receiver. if this bit is set to a 1, the crc generator and receiver are initialized to ones and if this bit is reset to a 0, they are initialized to 0s. this bit should be set to a 1 for most ccitt polynomials. bit 5 is cleared to a 0 upon a reset. bits 4,3 rx crc control bit 4 and bit 3 determine the type of crc remainder that will be checked at the end of a received frame. there is a 16-bit crc, and a 32-bit crc that the hdlc block can support. if both bit 4 and bit 3 are reset, bits 7 and 6 of the hdlc status register will be held to a 0. if both bit 4 and bit 3 are 1s, a special crc search mode is enabled where both bits 7 and 6 of the hdlc status register are enabled. this mode is used during a connection to determine which crc is used by the initiating modem. if the 16-bit crc remainder is not matched at the end of the received frame, then bit 6 of the hdlc status register is set. if the 32-bit crc remainder is not matched at the end of the received frame, then bit 7 of the hdlc status register is set. once the correct crc type is established during a connection, either bit 4 or bit 3 should be set to a 1 enabling the appropriate invalid crc status bit. bit 4 bit 3 crc type 0 0 no crc check 0 1 enable crc16 status 1 0 enable crc32 status 1 1 enable crc16 status and crc32 status bit 2 txcrc control bit 2 controls the crc type to be transmitted. if bit 2 is reset to a 0, a 16-bit crc will be transmitted with the send crc command. if bit 2 is set to a 1, a 32-bit crc will be transmitted. bit 1 zero insert/delete control when bit 1 is set to a 1, a 0 will be transmitted if either the send data or send crc bits of the hdlctx control are set after five consecutive 1s have been transmitted. also, when this bit is set, a 0 will be removed from the received data stream if it immediately follows a pattern of a 0 followed by five consecutive ones. if bit 1 is reset to a 0, no 0s will be inserted during transmission, and no 0s will be deleted during reception. bit 1 is cleared to a 0 upon a reset. bit 0 hdlc interrupt enable when bit 0 is reset to a 0, the hdlc will be prevented from generating an interrupt. the status bits that indicate the source of the interrupt can still be set allowing the hdlc block to be serviced in a polled mode. bit 0 is cleared to a 0 upon reset.
73M2910L microcontroller 16 hdlc control registers (continued) hdlc tx control register (htxc) sfr address 0c2h byte addressable reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 div16 clk send abort send crc send data send flag this register is used to control the source of data that appears on the ptxd pin. bits are shifted out on every rising edge of the ptxclk pin input. if no control bits are set, or more than one tx control bit is set, the ptxd pin will go to a binary 1. bits 7-5 always 0 bit 4 16x clock select under normal synchronous operation, the ptxclk and prxclk are used to receive and transmit data prxd and ptxd. the clock rate is equal to the data rate. in asynchronous modes, a clock 16 times the bit rate is provided at ptxclk and prxclk. when bit 4 is set to a 1 during asynchronous operation, the clocks at the ptxclk and prxclk input pins are divided by 16 to provide transmit and receive shift clocks. an internal clock for sampling incoming prxd data is synchronized by detecting any edge on the prxd data pin. the rising edge of this internal clock, used to sample incoming data, is delayed from the falling data edge by 8 prxclk periods and will continue at this phase and at a prxclk/16 frequency until another prxd edge is detected. if bit 4 is reset to a 0, the rising edge of ptxclk is used to sample the data at prxd, and the falling edge of ptxclk is used to shift new data onto ptxd. bit 3 abort when bit 3 is set to a 1, a series of consecutive ones will immediately be transmitted through the ptxd pin on every falling edge of ptxclk. the message will have been aborted after 2 tx ready interrupts are received. no zeros will be inserted during the abort transmission. bit 2 send crc when bit 2 is set, the bytes in the tx crc generator will be inverted and serially transmitted to the ptxd output on the falling edge on ptxclk as soon as the present data byte transmission is completed. if bit 1 of the hdlc control register is a 0, a 0 will be inserted into the crc data stream after five consecutive ones are transmitted. as soon as the last bit of the crc is sent, a series of flags will be automatically sent until another tx control bit is set. no tx ready interrupts will be generated during the transmission of the crc bytes. a tx ready interrupt will be generated as the first bit of each flag byte is transmitted indicating that the crc transmission has been completed. this should be cleared by a dummy write to the tx data register. bit 1 send data when bit 1 is set, the data is the tx data register will be serially transmitted through the ptxd pin on every falling edge of ptxclk, lsb first. if bit 1 of the hdlc control register is a 0, a 0 will be inserted into the data stream after five consecutive 1s are transmitted. after all eight data register bits have been sent, the hdlc will continue to send data by loading the parallel serial transmit register with new transmit register data, unless either a tx underrun is detected or one of the other tx control bits has been set. this bit will be cleared by the hdlc circuitry as soon as a tx underrun is detected. a txrdy interrupt will be generated as the first data of each data byte is transmitted. bit 1 will be cleared to a 0 upon a reset.
73M2910L microcontroller 17 bit 0 send flag when bit 0 is set, a pattern of 7e will be transmitted to the ptxd output as soon as either the next data byte or crc has completed transmission. no 0s will be inserted during the flag transmission. when bit 0 is reset back to a 0, the hdlc circuitry will complete the flag byte in progress and then transmit according to bits in the tx control register. tx ready interrupts will be generated as each byte of flag transmission is initiated. hdlc status register (hstat) sfr address 0c3h byte addressable read only register reset state 00h if any of the hdlc status bits are set, bit 1 of the hdlc interrupt register (new status) will be set if the corresponding bit in the hdlc interrupt enable register is set. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inval crc32 inval crc16 tx undrn rx ovrn inval flag abort det idle det flag det bit 7 invalid crc 32 bit 7 will be set if the crc search mode or the 32-bit crc is enabled by the hdlc control register and an incorrect remainder for the 32-bit crc is detected at the last received byte prior to receiving a flag. bit 7 will by cleared upon a reset and is cleared by a read of the hdlc stat register. bit 6 invalid crc 16 bit 6 will be set if the crc search mode or the 16-bit crc is enabled by the hdlc control register and an incorrect remainder for the 16-bit crc is detected at the last received byte prior to receiving a flag. bit 6 will by cleared upon a reset and is cleared by a read of the hdlc stat register. bit 5 tx underrun when bit 5 is set, a transmit underrun condition has been detected. this is a condition where the hdlc has finished transmitting a message byte, but no new data has been loaded into the tx data register, and no other transmit control bit has been set. this bit will be set only if the send data bit, bit 1 of the tx control register is set. the transmit data is double buffered since the tx data register is downloaded into a tx serial register when the hdlc begins to transmit a new data byte. at the time of loading the tx serial register, a tx ready interrupt is generated. this interrupt must be serviced by either loading a new data byte (the next data byte to be transmitted) into the tx data register, or by setting another tx control bit, before the current data byte has completed transmission (at which point another tx ready interrupt would be generated). if a tx underrun is detected, the hdlc will abort the current transmission by sending continuous ones and will reset the send data control bit in the tx control register. bit 5 will by cleared upon a reset and is cleared by a read of the hdlc stat register.
73M2910L microcontroller 18 hdlc status register (hstat) sfr address 0c3h (continued) bit 4 rx overrun when bit 4 is set, a receive overrun condition has been detected. this is a condition where the hdlc has received a new byte, but the last received data byte has not yet been read from the rx data register. as soon as a new data byte has been received in an eight-bit serial register, it is loaded into the rx data register and a new rx data interrupt is generated. if this interrupt is not serviced by reading the rx data register during the time another new data byte is received, the rx overrun status bit will be set. the new received data will not overwrite the older unread data. bit 4 will by cleared upon a reset and is cleared by a read of the hdlc stat register. bit 3 invalid flag when bit 3 is set, an invalid flag has been detected. this is a condition where a 7e pattern with no inserted 0s is detected, and this pattern did not originate on a byte boundary. note, two consecutive flags may share a 0, so that the second (or subsequent) flag may not appear to be on a byte boundary. this condition does not result in an invalid flag indication. bit 3 will by cleared upon a reset and is cleared by a read of the hdlc stat register. bit 2 abort detect when bit 2 is set, an abort condition has been detected. this is a condition where seven consecutive ones, with no inserted zeros, are received after an active state. bit 2 will be cleared upon a reset and is cleared by a read of the hdlc stat register. bit 1 idle detect when bit 1 is set, the first indication of an idle state is detected. an idle state is declared when 15 consecutive ones, with no inserted zeros, are received after an active state. bit 1 will be cleared upon a reset and is cleared by a read of the hdlc stat register. bit 0 flag detect when bit 0 is set, the hdlc has received a 7e pattern with no inserted 0?s. bit 0 will by cleared upon a reset and is cleared by a read of the hdlc stat register. hdlc interrupt enable register (hie) sfr address 0c4h byte addressable reset state 00h if the bit is set, the corresponding interrupt source is enabled. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx rdy ie rx rdy ie tx rdy en rx rdy en inval flg ie abort ie idle ie flag ie
73M2910L microcontroller 19 bit 7 transmitter ready interrupt enable when bit 7 is set, an hdlc interrupt will be generated if bit 0 (tx rdy) of the hdlc interrupt register is also set. if bit 7 is reset to a 0, no hdlc interrupt indication will be given as tx rdy is set. this interrupt enable allows the tx rdy to be a polled bit. note that bit 5 of this register is a pre-mask to the tx rdy bit, that is, it will prevent the tx rdy bit from ever being set. bit 6 receiver ready interrupt enable when bit 6 is set, an hdlc interrupt will be generated if bit 1 (rx rdy) of the hdlc interrupt (hint) register is also set. if bit 6 is reset to a 0, no hdlc interrupt indication will be given as rx rdy is set. this interrupt enable allows the rx rdy to be a polled bit. note that bit 4 of this register is a pre-mask to the rx rdy bit, that is, it will prevent the rx rdy bit from ever being set. bit 5 transmit ready enable bit 5 is used to enable the tx rdy and tx underrun interrupt sources. when bit 5 is set, the transmitter ready indication will set bit 0 of the hdlc interrupt register. the tx rdy indication will go active as the first bit of a message byte is being transmitted, except during crc transmission. also, if this bit is set, the tx underrun condition will result in a new status interrupt. if bit 5 is reset to a 0, bit 0 of the hdlc interrupt register will not be set, and no corresponding hdlc interrupt will be generated. also, a tx underrun condition, as indicated by bit 5 of the hdlc status register, will not result in an hdlc interrupt or in setting the new status interrupt bit. bit 4 receiver ready enable bit 4 is used to enable the rx rdy and rx overrun interrupt sources. when bit 4 is set, the receiver ready indication will set bit 1 of the hdlc interrupt (hint) register. the rx rdy indication will go active when a data byte (a byte that is not a flag, idle, or an abort pattern) is loaded into the rx data register. also, if this bit is set, the rx overrun condition will result in a new status interrupt. if bit 4 is reset to a 0, bit 1 of the hdlc interrupt register will not be set, and no corresponding hdlc interrupt will be generated. also, a rx overrun condition, as indicated by bit 4 of the hdlc status (hstat) register, will not result in a hdlc interrupt or in setting the new status interrupt bit. bit 3 invalid flag interrupt enable when bit 3 is set, a hdlc interrupt will be generated if bit 3 (invalid flag) of the hdlc status (hstat) register is also set. if bit 3 is reset to a 0, bit 2 (new status) of the hdlc interrupt (hint) register will not be set as a result of an invalid flag boundary detection and no hdlc interrupt will be generated. bit 2 abort detect interrupt enable when bit 2 is set, a hdlc interrupt will be generated if bit 2 (abort detect) of the hdlc status (hstat) register is also set. if bit 2 is reset to a 0, bit 2 (new status) of the hdlc interrupt (hint) register will not be set as a result of an abort pattern detection and no hdlc interrupt will be generated. bit 1 idle detect interrupt enable when bit 1 is set, an hdlc interrupt will be generated if bit 1 (idle detect) of the hdlc status (hstat) register is also set. if bit 1 is reset to a 0, bit 2 (new status) of the hdlc interrupt (hint) register will not be set as a result of an idle pattern detection and no hdlc interrupt will be generated.
73M2910L microcontroller 20 hdlc interrupt enable register (hie) sfr address 0c4h (continued) bit 0 flag detect interrupt enable when bit 0 is set, a hdlc interrupt will be generated if bit 0 (flag detect) of the hdlc status (hstat) register is also set. if bit 0 is reset to a 0, bit 2 (new status) of the hdlc interrupt (hint) register will not be set as a result of a flag pattern detection and no hdlc interrupt will be generated. hdlc interrupt source register (hint) sfr address 0c5h byte addressable read only register reset state 00h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000new status rxrdy txrdy this register is used to determine the source of hdlc interrupts. if one or more of these register bits are set, the corresponding hdlc interrupt will go active if bit 0 of the hdlc control 1 (hdlc1) register is set to a 1. bit 2 new status when bit 2 is set, an unmasked hdlc status bit from the hdlc status (hstat) register is set. bit 2 will by cleared upon a reset and is cleared by a read of the hdlc status register. bit 1 rx ready when bit 1 is set, a new received byte has been loaded into the rx data (rxd) register. note, received bits that are flag, abort, or idle patterns are not considered data, and will not be loaded into the rx data register. all inserted 0s have been removed from this byte. the rx data register must be read prior to the completed reception of the next data byte. bit 1 will by cleared upon a reset and is cleared by a read of the rx data register. bit 0 tx ready bit 0 is set if any hdlc tx control (htxc) bits 3:0 are set as the first bit of data, flag or an idle byte is being transmitted. while transmitting the current byte, the hdlc state machines are ready for commands pertaining to the next byte to be transmitted. a new data byte must be loaded into the tx data (txd) register to clear the tx ready status bit. bit 0 will by cleared upon a reset and is cleared by writing to the tx data register.
73M2910L microcontroller 21 rx data register (rxd) sfr address 0c6h byte addressable read only register reset state xxh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rx dat7 rx dat6 rx dat5 rx dat4 rx dat3 rx dat2 rx dat1 rx dat0 bits 7-0 received data byte bit 7 through bit 0 is the received data byte (lsb is received first) with all inserted 0s removed. a data ready interrupt will be generated when a new data byte is received. reading this register will clear the data ready interrupt. tx data register (txd) sfr address 0c7h byte addressable write only register reset state xxh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tx dat7 tx dat6 tx dat5 tx dat4 tx dat3 tx dat2 tx dat1 tx dat0 bits 7-0 transmit data byte bit 7 through bit 0 will be transmitted at the next byte boundary (lsb first) if the hdlc tx control send data bit is set. the hdlc will insert all necessary 0s. a tx ready interrupt will be generated when a new data byte can be loaded into the tx data register. writing this register will clear the tx ready interrupt.
73M2910L microcontroller 22 register description (continued) crc generation figure 3: ccitt type ccitt type the crc check field is generated by the transmitter. the computation starts with the first transmitted bit after the opening flag and stops at the last data bit prior to the frame check sequence bytes, and excludes inserted 0s. the crc generating logic is initialized to all ones. the bits are shifted in and operated on by the generating polynomial, x 16 + x 12 + x 5 + 1. during crc transmission, the bytes in the crc generating logic are inverted and transmitted, high order bit first. the receiver also initializes its crc computation logic to all ones after the beginning flag. its polynomial generator (also x 16 + x 12 + x 5 + 1) should see the same value as the transmitter?s polynomial generator as the last data bit is received. note the receiver?s polynomial generator does not process inserted 0s. after the bytes are received in the frame check sequence, a remainder of 1111 0000 1011 1000 (x 0 through x 15 , respectively) should be detected in the receiver?s polynomial generator. if this is not the case, it is assumed that the preceding frame was in error and an invalid crc is declared. set compute data and2 ccitt 16 bit crc x 16 + x 12 + x 5 + 1 mux out c 8 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15
73M2910L microcontroller 23 figure 4: crc 16 crc 16 the crc check field is generated by the transmitter. the computation starts with the first transmitted bit after the opening flag and stops at the last data bit prior to the frame check sequence bytes, and excludes inserted 0s. the crc generating logic is initialized to all 0s. the bits are shifted in and operated on by the generating polynomial, x 16 + x 12 + x 5 + 1. during crc transmission, the bytes in the crc generating logic are transmitted, high order bit first. the receiver also initializes its crc computation logic to all ones after the beginning flag. its polynomial generator (also x 16 + x 12 + x 5 + 1) should see the same value as the transmitter?s polynomial generator as the last data bit is received. note the receiver?s polynomial generator does not process inserted 0s. after the bytes are received in the frame check sequence, a remainder of 1111 0000 1011 1000 should be detected in the receiver?s polynomial generator. if this is not the case, it is assumed that the preceding frame was in error and an invalid crc is declared. reset (option to set) compute data and2 c 8 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 mux out crc 16 x 16 + x 15 + x 2 + 1
73M2910L microcontroller 24 crc generation (continued) figure 5: 32-bit crc crc 32 the crc check field is generated by the transmitter. the computation starts with the first transmitted bit after the opening flag and stops at the last data bit prior to the frame check sequence bytes, and excludes inserted 0s. the crc generating logic is initialized to all ones. the bits are shifted in and operated on by the generating polynomial, x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1. during crc transmission, the bytes in the crc generating logic are inverted and transmitted, high order bit first. the receiver also initializes its crc computation logic to all ones after the beginning flag. its polynomial generator should see the same value as the transmitter?s polynomial generator as the last data bit is received. note the receiver?s polynomial generator does not process inserted 0s. after the bytes are received in the frame check sequence, a remainder of 1101 1110 1011 1011 0010 0000 1110 0011 (x 0 through x 32 , respectively) should be detected in the receiver?s polynomial generator. if this is not the case, it is assumed that the preceding frame was in error and an invalid crc is declared. set compute data and2 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 16 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 17 c 18 c 19 c 20 c 21 c 22 c 23 c 24 c 25 c 26 c 27 c 28 c 29 c 30 c 31 mux out crc polynomial x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1
73M2910L microcontroller 25 pin description name type description psen o program store enable. this output occurs only during a fetch to external program memory. reset i input which is used to initialize the processor. vnd gnd negative digital voltage ground oscin i crystal input for internal oscillator, also input for external source. oscout o crystal oscillator output. vpd i positive digital voltage (+5v digital supply) clkout1 o clock output programmable either osc/2, osc/1 or logic 0. clkout2 o clock output 1.8432 mhz clock for an external uart given an oscillator frequency of 11.0592 mhz, 22.1184 mhz, 18.432 mhz, or 13.824 mhz. txd i serial input port to 73M2910L from dte same as rxd uart input. rxd o serial output port of 73M2910L uart to dte. ptxclk i input clock used to transmit data ptxd. ptxd o hdlc packetizer tx output. this pin can also be programmed to the dte?s txd output (clear channel) or the value written into bit 6 of the hdlc control register. connects to modem device txd. prxclk i input clock used to receive data prxd. prxd i serial input port (from modem device) to hdlc packetizer. int ( ) )- int ( @ ) i external interrupt 0,1 and 2. usr1.0 - usr1.7 i/o usr programmable i/o port. usr2.0 - usr2.7 i/o usr programmable i/o port. usr3.0 - usr3.7 i/o usr programmable i/o port. if the bank select feature is chosen, usr (7) acts as address bit 17 and usr3 data bit 7 is ignored. register bnksel bit 2 (bsen) enables bank select, bit 1 (bs1) and bit 0 (bs0) select the appropriate bank. usr4.0 - usr4.7 i/o usr programmable i/o port also chip select enable. usr5.0 - usr5.1 i/o general purpose input port, can also be used for wakeup. rd o output strobe activated during a bus read. can be used to enable data onto the bus from an external device. used as a read strobe to external data memory. wr o output strobe during a bus write. used as a write strobe to external data memory. ale o address latch enable output pulse for latching the low byte of the address during accesses to external memory. ad(0)-ad(7) i/o data bus lines-i/o for devices that require multiplexed address and data bus. a(0)-a(15) o address bus lines-output latched address for devices that require separate data and address bus. no connects(nc) no connections, leave open. not a user pin.
73M2910L microcontroller 26 memory maps figure 6: memory map figure 7: 128k of bank-selected program memory ffffh 0100h ffh 00h ffh ffh 80h 00h 80h 7fh external ram (movx data, addr) on chip externally addressed memory mapped register (movx data, addr) internal ram indirect addressing only (mov @ ri) sfrs direct addressing only (mov data, addr) direct & indirect addressing (mov data, addr) (mov @ ri) bank 3 bank 3 bank 3 address 32k - 64k bank 2 bank 2 address 32k - 64k bank 2 bank 1 address 32k - 64k bank 1 bank 1 bank 0 address 0 - 32k bank 0 address 0 - 32k bank 0 address 0 - 32k bank 1 selected bank 2 selected bank 3 selected 96k - 128k 64k - 96k 32k - 64k 0 - 32k
73M2910L microcontroller 27 figure 8: memory mapped registers figure 9: 73M2910L sfr map address locations 0008 - 00ff are reserved for future use usr3 dir3 bnksel usr4 dir4 csen 0000 0008 0007 000f usr5 f8 f0 e8 e0 d8 d0 c8 c0 b8 b0 a8 a0 98 90 88 80 ff f7 ef e7 df d7 cf c7 bf b7 af a7 9f 97 8f 87 b acc *usr2 *dir2 clk ctrl ip ie p2 scon sbuf *usr1 *dir1 *idir tcon th1 th0 tl1 tl0 tmod p0 sp dpl dph pcon *hdlc0 *hdlc1 *txc *hstat *hie *hint *hrxd *htxd t2con rcap2l rcap2h tl2 th2 psw *unique to the 73M2910L. there may not be an equivalent function on an 8032. bit addressable in this column
73M2910L microcontroller 28 electrical specifications absolute maximum ratings recommended conditions apply unless otherwise specified. parameter rating supply voltage -0.5 to +7.0v pin input voltage -0.5 to vcc +0.5v storage temperature -55 to +150 c recommended operating conditions supply voltage 3 to 5.5v oscillator frequency dc to 44 mhz operating temperature -40 to +85 c dc characteristics parameter condition min nom max unit input low voltage v il (except ptxclk, prxck, oscin, reset, test) -0.5 0.2 vcc 0.1 v input low voltage v il oscin, reset, test -0.5 0.2 vcc v input low voltage v il ptxclk, prxclk -0.5 0.2vcc- 0.3 v input high voltage v ih (except oscin, reset, test) 0.5 vcc vcc + 0.5 v input high voltage v ih oscin, reset, test 0.7 vcc vcc + 0.5 v output low voltage v ol (except oscout) iol = 3.2 ma 0.45 v output low voltage v olosc oscout iol = 1.5 ma 0.7 v output high voltage v oh (except oscout) ioh = -3.2 ma vcc - 0.45 v output high voltage v ohosc oscout ioh = 1.5 ma vcc - 0.7 v input leakage current i il vss < vin < vcc 10 a maximum power supply i dd 1 normal operation 22 mhz 30 pf/pin 40 ma maximum power supply i dd 2 idle mode 22 mhz 10 ma
73M2910L microcontroller 29 dc characteristics parameter condition min nom max unit maximum power supply idd3 power-down mode 10 a pin capacitance cio @1 mhz 10 pf ac timing the 73M2910L timing is very similar to the 8032 except in ad(7:0), the multiplexed address data port known as port 0 in the 8032. its timing has been altered somewhat to allow more address setup time for peripheral program rom and memory mapped peripherals. this is important for operation above 22 mhz. the 8032 has a ?dead? cycle of one oscillator period between the time psen goes high, indicating that the instruction rom will release the ad(7:0) bus, to the time the processor will assert address on the ad(7:0) bus. this dead time of one whole oscillator cycle has been shortened to approximately 15 ns after the psen (or rd) signal is sensed to be high. the timing specification for tpxiz and trhdz of a maximum of 20 ns can be violated at the expense of increased operating current. the 73M2910L will begin asserting the ad(7:0) bus approximately 20 ns after psen or rd go high. this should be ample time for the control signals in the peripheral device to turn off their pad drivers. if the peripheral device does not release the bus promptly, there will be a short time where there is contention on the ad(7:0) bus between the processor and peripheral. this should not prevent proper operation, but it will increase operating current slightly. external program memory read timing oscillator frequency fosc 0 44 mhz oscillator period tosc 22.7 ns ale pulse width tlhll 2tosc - 10 ns address valid to ale low tavll tosc ns address valid ale low tllax tosc - 10 ns ale low to psen low tllpl tosc - 10 ns psen pulse width low tplph 3tosc - 20 ns psen low to valid inst in tpliv 3tosc - 50 ns address to valid inst in taviv 6tosc - 32 ns input instr hold- psen high tpxix 0 ns psen instr float- psen high tpxiz 20+ ns psen low to address highz tplaz 10 ns
73M2910L microcontroller 30 figure 10: external program memory read cycle oscin ale ad(7:0) a(15:0) tosc tlhll tllpl tplaz a0-a7 instr in tllax tpliv taviv tavll tpxix tpxiz high z tplph
73M2910L microcontroller 31 ac timing (continued) external data read and write timing parameter condition min nom max unit rd pulse width trlrh 6tosc - 20 ns wr pulse width twlwh 6tosc - 20 ns rd low to valid data in trldv 5tosc - 50 ns data hold after rd trhdx 0 ns data float after rd trhdz 20+ ns ale low to valid data in tlldv 8tosc - 50 ns ale low to rd or wr low tllwl 3tosc - 20 3tosc + 20 ns data valid to wr low tqvwx tosc ns data hold after wr high twhqx tosc - 10 ns rd low to address float trlaz 10 ns
73M2910L microcontroller 32 electrical specifications (continued) figure 11: external data memory write cycle figure 12: external data memory read cycle tosc tllwl twlwh twhqx tqvwx a0-a7 instr in a0-a7 data out a0-a7 oscin ale ad (7:0) a (15:0) tosc tllwl tlldv trhdz trhdx trlaz trldv a0-a7 instr in a0-a7 data in oscin ale ad (7:0) a (15:0) trlrh
73M2910L microcontroller 33 note: the 73d2248a device set is comprised of the 73M2910L and 73k224l. figure 13: modem block diagram user interface 73d2248a device set telephone interface ag1 ag0 txa rxa txa rxa
73M2910L microcontroller 34 electrical specifications (continued) figure 14: display and user interface mr tr tr mr vcc r32 2.4k r33 2.4k d6 td rd r39 2.4k r34 2.4k d7 d8 hs aa cd oh cd aa r35 2.4k r36 2.4k d9 d10 oh hs r37 2.4k r38 2.4k d11 d12 exclk 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 p1 connector db25 note: 1 f tantalums c13 1 f c14 1 f c1+ 21 c1- 23 c2+ 24 c2- 25 vcc 20 v- 26 ta1out 1 ta2out 2 ta3out 3 ta4out 4 ra1in 8 ra2in 7 ra3in 6 ra4in 5 tb1out 44 tb2out 43 tb3out 42 tb4out 41 rb1in 37 rb2in 38 rb3in 39 rb4in 40 v+ 22 ta1in 14 ta2in 15 ta3in 16 ta4in 17 ra1out 10 ra2out 11 ra3out 12 ra4out 13 tb1in 31 tb2in 30 tb3in 29 tb4in 28 rb1out 35 rb2out 34 rb3out 33 rb4out 32 enta 18 enra 9 ent 27 enr 36 gnd 19 u8 max248 c15 1 f c16 1 f vcc cts dcd ri rxd exclk gnd gnd dtr dcd ri rate rts rxd cts dsr txclk rxclk gnd txclk rxclk rts dtr txd dsr vcc txd gnd
73M2910L microcontroller 35 figure 15: telephone interface

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